1. Field of the Invention
The invention relates to a nonvolatile semiconductor memory device in which control gate electrodes and interlayer insulating films are alternately stacked and a method for manufacturing the same.
2. Background Art
Thus far, nonvolatile semiconductor memory devices such as flash memory have been fabricated by integrating elements two-dimensionally on the surface of a silicon substrate. In such flash memories, the only thing to reduce cost per one bit to increase memory capacity is to lower the dimension of each element to allow miniaturization. However, such miniaturization is becoming difficult these days in terms of cost and technique.
Improvement in photolithographic technique is necessary in order to promote the miniaturization of elements. Current ArF immersion exposure technique has modification limits of rules near 40 nm, and employing an EUV (extreme ultraviolet) exposure apparatus is necessary for further miniaturization. However, EUV exposure apparatuses are very high in cost and not practical. Even if miniaturization is achieved by using an EUV exposure apparatus, it is expected that breakdown voltage between elements and the like reaches the physical limit unless driving voltage also is scaled, and there is a high possibility that operation as a device becomes difficult.
Therefore, many ideas of integrating elements three-dimensionally are proposed as a technique for breaking through the limit of high integration. However, since common three-dimensional devices require several lithography steps for each layer, the increased cost due to the increased number of lithography steps cancels the reduced cost due to the reduced area of a silicon substrate. Therefore, cost reduction is difficult even if elements are integrated three-dimensionally.
In view of this problem, the inventor and others have proposed a three-dimensional stacked memory of collective-processing type (for example, see JP-A 2007-266143 (Kokai)). In this technique, electrode films and insulating films are alternately stacked on a silicon substrate to form a stacked body, and then a through-hole is formed in the stacked body by collective processing. Then, a charge storage layer is formed on the side face of the through-hole and silicon is buried in the through-hole to form a silicon pillar. Thereby, a MONOS (metal-oxide-nitride-oxide-silicon) type transistor is formed at the intersection of each electrode film and the silicon pillar, and this forms a memory cell.
In this three-dimensional stacked memory of collective-processing type, a charge can be transferred between each electrode film and each silicon pillar by controlling the electric potentials of the electrode film and the silicon pillar, and thereby information can be recorded. According to this technique, a plurality of electrode films are stacked on the silicon substrate, and thereby chip area per one bit can be reduced, serving to reduce the cost of a wafer. Furthermore, the three-dimensional stacked memory can be fabricated by processing the stacked body collectively; therefore, the number of lithography steps does not increase even if the number of stacked layers increases, and an increase in manufacturing cost can be suppressed.
However, the three-dimensional stacked memory of collective-processing type thus fabricated has a problem that the erasing speed is slow because the memory cell is configured by a MONOS type transistor. Furthermore, since the charge storage layer is continuously formed in the through-hole, there is a problem that interference between memory cells increases as miniaturization progresses.